MCM6226BB

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM6226BB/D 128K x 8 Bit Static Random Access Memory The MCM6226BB is a 1,048,576 bit static random access memory organized as 131,072 words of 8 bits. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6226BB is equipped with both chip enable (E1 and E2) and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems. The MCM6226BB is available in 300 mil and 400 mil, 32 lead surface–mount SOJ packages. Single 5 V ± 10% Power Supply Fast Access Times: 15/17/20/25/35 ns Equal Address and Chip Enable Access Times All Inputs and Outputs are TTL Compatible Three State Outputs Low Power Operation: 190/180/165/150/130 mA Maximum, Active AC BLOCK DIAGRAM MCM6226BB XJ PACKAGE 400 MIL SOJ CASE 857A–02 EJ PACKAGE 300 MIL SOJ CASE 857–02 PIN ASSIGNMENT NC A A A A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A E2 W A A A A G A E1 DQ DQ DQ DQ DQ A A A A A A A A A ROW DECODER MEMORY MATRIX 512 ROWS x 2048 COLUMNS A A A A A A DQ DQ DQ VSS DQ DQ INPUT DATA CONTROL COLUMN I/O COLUMN DECODER PIN NAMES A . . . . . . . . . . . . . . . . . . . . Address Inputs W . . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . Output Enable E1, E2 . . . . . . . . . . . . . . . . Chi...