MCM6229BB

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM6229BB/D Product Preview MCM6229BB XJ PACKAGE 400 MIL SOJ CASE 810–03 256K x 4 Bit Static Random Access Memory The MCM6229BB is a 1,048,576 bit static random access memory organized as 262,144 words of 4 bits. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6229BB is equipped with both chip enable (E) and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems. The MCM6229BB is available in 300 mil and 400 mil, 28 lead surface–mount SOJ packages. Single 5 V ± 10% Power Supply Fast Access Times: 15/17/20/25/35 ns Equal Address and Chip Enable Access Times All Inputs and Outputs are TTL Compatible and LVTTL Compatible Three State Outputs Low Power Operation: 155/150/135/130/110 mA Maximum, Active AC BLOCK DIAGRAM A A A A A A A A A ROW DECODER MEMORY MATRIX 512 ROWS x 2048 COLUMNS EJ PACKAGE 300 MIL SOJ CASE 810B–03 PIN ASSIGNMENTS A A A A A A A A A A A E G VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A A A A A A A NC* DQ DQ DQ DQ W DQ INPUT DATA CONTROL DQ A A A COLUMN I/O COLUMN DECODER PIN NAMES A . . . . . . . . . . . . . . . . . . . . Address Inputs W . . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . Output Enable E . . . . . . . . . . . . . ....