MCM62Y308

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM62Y308/D Advance Information MCM62Y308 J PACKAGE 300 MIL SOJ CASE 857–02 Synchronous Line Buffer: 8K x 8 Bit Fast Static Dual Ported Memory With IEEE Standard 1149.1 Test Access Port and Boundary–Scan (JTAG) The MCM62Y308 is a synchronous, dual ported memory organized as 8,192 words of 8 bits each, fabricated using Motorola’s double–metal, double–poly, 0.65 µm CMOS process. It is intended for high speed video or other applications which process data on a line–by–line basis. Through the use of a single clock and port control inputs, separate read and write data ports provide simultaneous access to a common memory array. Simultaneous read/write access to the same address location is also allowed, with old data being read followed by a write of the new data. This allows multiple devices to be cascaded with the output of one directly driving the input of another. In this configuration the data stream can be tapped at strategic interconnect points to perform various digital filtering functions. Since there are no external address inputs, separate internal read and write address counters are provided as a means of indexing the memory array. These counters are preloaded and then selectively incremented or decremented by asserting read enable (RE) and write enable (WE) inputs, allowing cycle to cycle control. The address counters can be reloaded back to their initial values through the use of the read reload (RR) an...