MCM67A618B

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67A618B/D Advance Information MCM67A618B 64K x 18 Bit Asynchronous/ Latched Address Fast Static RAM The MCM67A618B is a 1,179,648 bit latched address static random access memory organized as 65,536 words of 18 bits. The device integrates a 64K x 18 SRAM core with advanced peripheral circuitry consisting of address and data input latches, active low chip enable, separate upper and lower byte write strobes, and a fast output enable. This device has increased output drive capability supported by multiple power pins. Address, data in, and chip enable latches are provided. When latch enables (AL for address and chip enables and DL for data in) are high, the address, data in, and chip enable latches are in the transparent state. If latch enables are tied high the device can be used as an asynchronous SRAM. When latch enables are low the address, data in, and chip enable latches are in the latched state. This input latch simplifies read and write cycles by guaranteeing address and data–in hold time in a simple fashion. DQ9 Dual write enables (LW and UW) are provided to allow individually DQ10 writeable bytes. LW controls DQ0 – DQ8 (the lower bits) while UW VCC controls DQ9 – DQ17 (the upper bits). VSS Six pair of power and ground pins have been utilized and placed on DQ11 the package for maximum performance. DQ12 The MCM67A618B will be available in a 52–pin plastic leaded chip DQ13 carrier (PLCC). DQ14 This device ...