MCM67B618A

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67B618A/D 64K x 18 Bit BurstRAM™ Synchronous Fast Static RAM With Burst Counter and Self–Timed Write The MCM67B618A is a 1,179,648 bit synchronous fast static random access memory designed to provide a burstable, high–performance, secondary cache for the i486™ and Pentium™ microprocessors. It is organized as 65,536 words of 18 bits. The device integrates input registers, a 2–bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (A0 – A15), data inputs (D0 – D17), and all control signals except output enable (G) are clock (K) controlled through positive–edge– triggered noninverting registers. Bursts can be initiated with either address status processor (ADSP) or DQ9 address status cache controller (ADSC) input pins. Subsequent burst DQ10 addresses can be generated internally by the MCM67B618A (burst VCC sequence imitates that of the i486 and Pentium) and controlled by the burst VSS address advance (ADV) input pin. The following pages provide more deDQ11 tailed information on burst controls. DQ12 Write cycles are internally self–timed and are initiated by the rising edge DQ13 of the clock (K) input....