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MCM67J618 Datasheet

Part Number MCM67J618
Manufacturers Motorola
Logo Motorola
Description 64K x 18 Bit BurstRAM Synchronous Fast Static RAM
Datasheet MCM67J618 DatasheetMCM67J618 Datasheet (PDF)

MOTOROLA • SEMICONDUCTOR TECHNICAL DATA Product Preview 64K x 18 Bit BurstRAMTM Synchronous Fast Static RAM With Burst Counter and Registered Outputs MCM67J618 The MCM67J618 is a 1,179,648 bit synchronous static random access memory de- signed to provide a burstable, high-performance, secondary cache for the i486™ and Pentium™ microprocessors. It is organized as 65,536 words of 18 bits, fabricated with Motorola's high-performance silicon-gate BiCMOS technology. The device integrates input FN.

  MCM67J618   MCM67J618






Part Number MCM67J618B
Manufacturers Motorola
Logo Motorola
Description 64K x 18 Bit BurstRAM Synchronous Fast Static RAM
Datasheet MCM67J618 DatasheetMCM67J618B Datasheet (PDF)

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67J618B/D Product Preview MCM67J618B 64K x 18 Bit BurstRAM™ Synchronous Fast Static RAM With Burst Counter and Registered Outputs The MCM67J618B is a 1,179,648 bit synchronous static random access memory designed to provide a burstable, high–performance, secondary cache for the i486™ and Pentium™ microprocessors. It is organized as 65,536 words of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS technolo.

  MCM67J618   MCM67J618







64K x 18 Bit BurstRAM Synchronous Fast Static RAM

MOTOROLA • SEMICONDUCTOR TECHNICAL DATA Product Preview 64K x 18 Bit BurstRAMTM Synchronous Fast Static RAM With Burst Counter and Registered Outputs MCM67J618 The MCM67J618 is a 1,179,648 bit synchronous static random access memory de- signed to provide a burstable, high-performance, secondary cache for the i486™ and Pentium™ microprocessors. It is organized as 65,536 words of 18 bits, fabricated with Motorola's high-performance silicon-gate BiCMOS technology. The device integrates input FNPACKAGE PLASTIC CASE 778 registers, a 2-bit counter, high speed SRAM, and high drive registered output drivers onto a single monolithic circuit for reduced parts count implementation of cache data RAM ap- plications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated func- PIN ASSIGNMENT tions for greater reliability. Addresses (AO - A15), data inputs (DO - D17), and all contr.


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