MCM67M518

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67M518/D 32K x 18 Bit BurstRAM™ Synchronous Fast Static RAM With Burst Counter and Self–Timed Write The MCM67M518 is a 589,824 bit synchronous static random access memory designed to provide a burstable, high–performance, secondary cache for the MC68040 and PowerPC™ microprocessors. It is organized as 32,768 words of 18 bits, fabricated using Motorola’s high–performance silicon–gate BiCMOS technology. The device integrates input registers, a 2–bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (A0 – A14), data inputs (DQ0 – DQ17), and all control signals, except output enable (G), are clock (K) controlled through positive–edge–triggered noninverting registers. Bursts can be initiated with either transfer start processor (TSP) or transfer start cache controller (TSC) input pins. Subsequent burst addresses are generated internally by the MCM67M518 (burst sequence imitates that of the MC68040 and PowerPC) and controlled by the burst address advance (BAA) input pin. The following pages provide more detailed information on burst controls. Write cycles are internally self–timed and are initiated by t...