MCM69Q536

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69Q536/D Advance Information MCM69Q536 32K x 36 Bit Synchronous Separate I/O SRAM The Motorola MCM69Q536 is a 1 Megabit static random access memory, organized as 32K words of 36 bits. It features separate data input and data output buffers and incorporates input and output registers on board with high speed SRAM. The MCM69Q536 allows the user to perform transparent writes and data pass through. Two data bus ports are provided — a data input (D) and a data output (Q) port. The synchronous design allows for precise cycle control with the use of an external single clock (K). Address port, data input (D0 – D35), data output (Q0 – Q35), write enable (W), chip enables (E1, E2), and pass–through enable (PT) are registered on the rising edge of clock (K). Any given cycle operates on only one address. However, for any cycle, reads and writes can be intermixed. Thus, one can perform a read, a write, or a combination read/ write during any one cycle. For a combination read/write, the contents of the array are read before the new data is written. By using the pass–through function, the output port Q can be made to reflect either the contents of the array or the data presented to the input port D. For read/write or a read cycle with G low, the Q port will output the contents of the array. However, if PT is asserted, the Q port will instead output the data presented at the D input port. Single ...