MM74C925

MM74C925 MM74C926 MM74C927 MM74C928 4-Digit Counters with Multiplexed 7-Segment Output Drivers October 1987 Revised January 1999 MM74C925 MM74C926 MM74C927 MM74C928 4-Digit Counters with Multiplexed 7-Segment Output Drivers General Description The MM74C925, MM74C926, MM74C927 and MM74C928 CMOS counters consist of a 4-digit counter, an internal output latch, NPN output sourcing drivers for a 7-segment display, and an internal multiplexing circuitry with four multiplexing outputs. The multiplexing circuit has its own free-running oscillator, and requires no external clock. The counters advance on negative edge of clock. A HIGH signal on the Reset input will reset the counter to zero, and reset the carry-out LOW. A LOW signal on the Latch Enable input will latch the number in the counters into the internal output latches. A HIGH signal on Display Select input will select the number in the counter to be displayed; a LOW level signal on the Display Select will select the number in the output latch to be displayed. The MM74C925 is a 4-decade counter and has Latch Enable, Clock and Reset inputs. The MM74C926 is like the MM74C925 except that it has a display select and a carry-out used for cascading counters. The carry-out signal goes HIGH at 6000, goes back LOW at 0000. The MM74C927 is like the MM74C926 except the second most significant digit divides by 6 rather than 10. Thus, if the clock input frequency is 10 Hz, the display would read tenths of seconds and minutes ...