MN101D06F

www.DataSheet4U.com MN101D06F , MN101D06G , MN101D06H Type ROM (× 8-bit) RAM (× 8-bit) Package Minimum Instruction Execution Time Interrupts With main clock operated When sub-clock operated MN101D06F 96 K 3K MN101D06G 128 K 4K QFP100-P-1818B *Lead-free MN101D06H 160 K 5K 0.1397 µ s (at 4.0 V to 5.5 V, 14.32 MHz) 71.5 µ s (at 3.0 V to 5.5 V fixed to 14.32 MHz internal frequency division) 61 µ s (at 2.2 V to 5.5 V, 32.768 kHz) RESET Runaway External 0 External 1 External 2 External 3 External 4 key input (P50 to 54) Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 6 Capstan FG Control HSW Cylinder(Drum) FG Servo V-sync Synchronous output OSD XDS Serial 0 Serial 1 Serial 2 A/D (common with PWM 4 reference frequency) OSD V-sync Timer counter 0: 16-bit × 1 (timer function, clock function [max. 2 s or max. 36 h at cascade-connecting with timer 6]) Clock source ····················· 1/2, (1/4,) 1/8, (1/16) of system clock frequency; overflow of timer counter 6; 1/512 of XI oscillation clock or OSC oscillation clock frequency Interrupt source ················ overflow of timer counter 0 Timer counter 1: 16-bit × 1 (timer function, linear timer counter function) Clock source ····················· 1/2, (1/4,) 1/8, (1/16) of system clock frequency; CTL signal Interrupt source ················ overflow of timer counter 1 Timer counter 2: 16-bit × 1 (timer function, input capture, duty judgment of CTL signal(VISS/VASS detection functi...