MPC2104P

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MPC2104P/D Product Preview 256KB/512KB BurstRAM™ Secondary Cache Modules for PowerPC™ PReP/CHRP Platforms The MPC2104P (256KB) and MPC2105P (512KB) are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. The MPC2104P and MPC2105P utilize synchronous BurstRAMs. The MPC2104P module is configured as 32K x 64 bits and uses two of the 3.3 V 32K x 32 data RAMs. The MPC2105P is configured as 64K x 64 bits and uses two of the 3.3 V 64K x 32 data RAMs. Both modules are in a 178 (89 x 2) pin DIMM format. For tag bits on the 2104P, a 5 V cache tag RAM configured as 8K x 14 for tag field plus 8K x 2 for valid and dirty status bits is used. For tag bits on the 2105P, a 5 V cache tag RAM configured as 16K x 14 for tag field plus 16K x 2 for valid and dirty status bits is used. Bursts can be initiated with the ADS signal. Subsequent burst addresses are generated internally to the BurstRAM by the CNTEN signal. Write cycles are internally self–timed and are initiated by the rising edge of the clock (CLKx) inputs. Writes are global with two inputs for reduced loading. Presence detect pins are available for auto configuration of the cache control. The module family pinout will support 5 V and 3.3 V components for a clear path to lower voltage and power sa...