Microcontrollers. MSP430F6720A Datasheet

MSP430F6720A Datasheet PDF

Part MSP430F6720A
Description Mixed-Signal Microcontrollers
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MSP430F6720A
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MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018
MSP430F673xA, MSP430F672xA Mixed-Signal Microcontrollers
1 Device Overview
1.1 Features
1
• Low Supply-Voltage Range:
3.6 V Down to 1.8 V
• Ultra-Low Power Consumption
– Active Mode (AM):
All System Clocks Active
265 µA/MHz at 8 MHz, 3.0 V, Flash Program
Execution (Typical)
140 µA/MHz at 8 MHz, 3.0 V, RAM Program
Execution (Typical)
– Standby Mode (LPM3):
Real-Time Clock (RTC) With Crystal, Watchdog,
and Supply Supervisor Operational, Full RAM
Retention, Fast Wake up:
1.7 µA at 2.2 V, 2.5 µA at 3.0 V (Typical)
– Off Mode (LPM4):
Full RAM Retention, Supply Supervisor
Operational, Fast Wake up:
1.6 µA at 3.0 V (Typical)
– Shutdown RTC Mode (LPM3.5):
Shutdown Mode, Active RTC With Crystal:
1.24 µA at 3.0 V (Typical)
– Shutdown Mode (LPM4.5):
0.78 µA at 3.0 V (Typical)
• Wake up From Standby Mode in 3 µs (Typical)
• 16-Bit RISC Architecture, Extended Memory, up to
25-MHz System Clock
• Flexible Power-Management System
– Fully Integrated LDO With Programmable
Regulated Core Supply Voltage
– Supply Voltage Supervision, Monitoring, and
Brownout
– System Operation From up to Two Auxiliary
Power Supplies
• Unified Clock System
– FLL Control Loop for Frequency Stabilization
– Low-Power Low-Frequency Internal Clock
Source (VLO)
– Low-Frequency Trimmed Internal Reference
Source (REFO)
– 32-kHz Crystals (XT1)
• One 16-Bit Timer With Three Capture/Compare
Registers
• Three 16-Bit Timers With Two Capture/Compare
Registers Each
• Enhanced Universal Serial Communication
Interfaces (eUSCIs)
– eUSCI_A0, eUSCI_A1, and eUSCI_A2
– Enhanced UART Supports Automatic Baud-
Rate Detection
– IrDA Encoder and Decoder
– Synchronous SPI
– eUSCI_B0
– I2C With Multiple Slave Addressing
– Synchronous SPI
• Password-Protected RTC With Crystal Offset
Calibration and Temperature Compensation
• Separate Voltage Supply for Backup Subsystem
– 32-kHz Low-Frequency Oscillator (XT1)
– Real-Time Clock
– Backup Memory (4 × 16 Bits)
• Three 24-Bit Sigma-Delta Analog-to-Digital
Converters (ADCs) With Differential PGA Inputs
• Integrated LCD Driver With Contrast Control for up
to 320 Segments in 8-Mux Mode
• Hardware Multiplier Supports 32-Bit Operations
• 10-Bit 200-ksps ADC
– Internal Reference
– Sample-and-Hold, Autoscan Feature
– Up to Six External Channels and Two Internal
Channels, Including Temperature Sensor
• Three-Channel Internal DMA
• Serial Onboard Programming, No External
Programming Voltage Needed
Device Comparison Summarizes the Available
Family Members
• Available in 100-Pin and 80-Pin LQFP Packages
• Single-Phase Electronic Watt-Hour Meter
Development Tool (Also See Tools and Software)
EVM430-F6736 - MSP430F6736 EVM for
Metering
Energy Measurement Design Center for
MSP430™ MCUs
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



MSP430F6720A
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018
www.ti.com
1.2 Applications
• Single-Phase Electronic Watt-Hour Meters
• Energy Monitoring
• Utility Metering
1.3 Description
The TI MSP family of ultra-low-power microcontrollers consists of several devices featuring different sets
of peripherals targeted for various applications. The architecture, combined with extensive low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device
features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to
maximum code efficiency. The DCO allows the device to wake up from low-power modes to active mode
in 3 µs (typical).
The MSP430F673xA and MSP430F672xA devices are microcontrollers with high-performance 24-bit
sigma-delta ADCs (three ADCs in MSP430F673xA and two ADCs in MSP430F672xA), a 10-bit ADC, four
eUSCIs (three eUSCI_A modules and one eUSCI_B module), four 16-bit timers, a hardware multiplier, a
DMA module, an RTC module with alarm capabilities, an LCD driver with integrated contrast control, an
auxiliary supply system, and up to 72 I/O pins in the 100pin devices and 52 I/O pins in the 80pin devices.
For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide.
PART NUMBER
Device Information(1)
PACKAGE
BODY SIZE(2)
MSP430F6736AIPZ
LQFP (100)
14 mm × 14 mm
MSP430F6736AIPN
LQFP (80)
12 mm × 12 mm
(1) For the most current part, package, and ordering information, see the Package Option Addendum in
Section 9, or see the TI website at www.ti.com.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
2 Device Overview
Copyright © 2015–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A
MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A



MSP430F6720A
www.ti.com
MSP430F6736A, MSP430F6735A, MSP430F6734A, MSP430F6733A
MSP430F6731A, MSP430F6730A, MSP430F6726A, MSP430F6725A
MSP430F6724A, MSP430F6723A, MSP430F6721A, MSP430F6720A
SLASE46A – FEBRUARY 2015 – REVISED OCTOBER 2018
1.4 Functional Block Diagrams
Figure 1-1 shows the functional block diagram for all device variants in the PZ package.
XIN XOUT
(32 kHz)
DVCC DVSS AVCC AVSS AUX1 AUX2 AUX3 RST/NMI
PA
P1.x P2.x
PB
P3.x P4.x
PC PD
P5.x P6.x P7.x P8.x
PE
P9.x
Unified
Clock
System
ACLK
SMCLK
MCLK
128KB
96KB
64KB
32KB
16KB
Flash
CPUXV2
and
Working
Registers
(25 MHz)
8KB
4KB
2KB
1KB
RAM
SYS
Watchdog
Port
Mapping
Controller
CRC16
MPY32
I/O Ports
P1, P2
2×8 I/Os
Interrupt,
Wakeup
PA
1×16 I/Os
I/O Ports
P3, P4
2×8 I/Os
I/O Ports
P5, P6
2×8 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
I/O Ports
P7, P8
2×8 I/Os
PD
1×16 I/Os
I/O Ports
P9
1×4 I/O
PE
1×4 I/O
EEM
(S: 3+1)
JTAG,
SBW
Interface
Port PJ
PJ.x
PMM
Auxiliary
Supplies
LDO
SVM, SVS
BOR
SD24_B
3 Channel
2 Channel
ADC10_A
LCD_C
REF
10 Bit
200 ksps
8-mux
Up to 320
Segments
Reference
1.5 V, 2.0 V,
2.5 V
RTC_C
TA0
Timer_A
3 CC
Registers
TA1
TA2
TA3
Timer_A
2 CC
Registers
eUSCI_A0
eUSCI_A1
eUSCI_A2
(UART,
IrDA,SPI)
eUSCI_B0
(SPI, I2C)
DMA
3 Channel
Copyright © 2016, Texas Instruments Incorporated
Figure 1-1. Functional Block Diagram - MSP430F673xAIPZ and MSP430F672xAIPZ
Figure 1-2 shows the functional block diagram for all device variants in the PN package.
XIN XOUT
(32 kHz)
DVCC DVSS AVCC AVSS AUX1 AUX2 AUX3 RST/NMI
PA
P1.x P2.x
PB
P3.x P4.x
PC
P5.x P6.x
Unified
Clock
System
ACLK
SMCLK
MCLK
128KB
96KB
64KB
32KB
16KB
Flash
8KB
4KB
2KB
1KB
RAM
DMA
3 Channel
SYS
Watchdog
Port
Mapping
Controller
CRC16
MPY32
I/O Ports
P1, P2
2×8 I/Os
Interrupt,
Wakeup
PA
1×16 I/Os
I/O Ports
P3, P4
2×8 I/Os
I/O Ports
P5, P6
2×8 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
CPUXV2
and
Working
Registers
(25 MHz)
EEM
(S: 3+1)
JTAG,
SBW
Interface
Port PJ
PJ.x
PMM
Auxiliary
Supplies
LDO
SVM, SVS
BOR
SD24_B
3 Channel
2 Channel
ADC10_A
LCD_C
REF
10 Bit
200 ksps
8 mux
Up to 320
Segments
Reference
1.5 V, 2.0 V,
2.5 V
RTC_C
TA0
Timer_A
3 CC
Registers
TA1
TA2
TA3
Timer_A
2 CC
Registers
eUSCI_A0
eUSCI_A1
eUSCI_A2
(UART,
IrDA, SPI)
eUSCI_B0
(SPI, I2C)
Copyright © 2016, Texas Instruments Incorporated
Figure 1-2. Functional Block Diagram - MSP430F673xAIPN and MSP430F672xAIPN
Copyright © 2015–2018, Texas Instruments Incorporated
Device Overview
Submit Documentation Feedback
Product Folder Links: MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A
MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A
MSP430F6720A
3







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