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MT29F1G08ABADAH4 Datasheet

Part Number MT29F1G08ABADAH4
Manufacturers Micron Technology
Logo Micron Technology
Description NAND Flash Memory
Datasheet MT29F1G08ABADAH4 DatasheetMT29F1G08ABADAH4 Datasheet (PDF)

Micron Confidential and Proprietary Preliminary‡ 1Gb x8, x16: NAND Flash Memory Features NAND Flash Memory MT29F1G08ABADAWP, MT29F1G08ABBDAH4, MT29F1G08ABBDAHC, MT29F1G16ABBDAH4, MT29F1G16ABBDAHC, MT29F1G08ABADAH4 Features • Open NAND Flash Interface (ONFI) 1.0-compliant1 • Single-level cell (SLC) technology • Organization – Page size x8: 2112 bytes (2048 + 64 bytes) – Page size x16: 1056 words (1024 + 32 words) – Block size: 64 pages (128K + 4K bytes) – Device size: 1Gb: 1024 blocks • Asynch.

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NAND Flash Memory

Micron Confidential and Proprietary Preliminary‡ 1Gb x8, x16: NAND Flash Memory Features NAND Flash Memory MT29F1G08ABADAWP, MT29F1G08ABBDAH4, MT29F1G08ABBDAHC, MT29F1G16ABBDAH4, MT29F1G16ABBDAHC, MT29F1G08ABADAH4 Features • Open NAND Flash Interface (ONFI) 1.0-compliant1 • Single-level cell (SLC) technology • Organization – Page size x8: 2112 bytes (2048 + 64 bytes) – Page size x16: 1056 words (1024 + 32 words) – Block size: 64 pages (128K + 4K bytes) – Device size: 1Gb: 1024 blocks • Asynchronous I/O performance – tRC/tWC: 20ns (3.3V), 25ns (1.8V) • Array performance – Read page: 25µs3 – Program page: 200µs (TYP, 3.3V and 1.8V)3 – Erase block: 700µs (TYP) • Command set: ONFI NAND Flash Protocol • Advanced command set – Program page cache mode5 – Read page cache mode5 – One-time programmable (OTP) mode – Read unique ID – Internal data move • Operation status byte provides software method for detecting – Operation completion – Pass/fail condition – Write-protect status • Internal data move operations supported within the device from which data is read • Ready/busy# (R/B#) signal provides a hardware method for detecting operation completion • WP# signal: write protect entire device • First block (block address 00h) is valid when shipped from factory with ECC. For minimum required ECC, see Error Management. • Block 0 requires 1-bit ECC if PROGRAM/ERASE cycles are less than 1000 • RESET (FFh) required as first command after poweron • Alternate method of device initialization .


2014-10-09 : B945    RK3026    SN74381    SN74481    M471B5674QH0    M471B5173QH0    M471B1G73QH0    M474B5173QH0    M474B1G73QH0    SG5127RD325693UU   


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