MT4LC4M16F5

4 MEG x 16 FPM DRAM DRAM MT4LC4M16F5 For the latest data sheet, please refer to the Micron Web site: www.micron.com/mti/msp/html/ datasheet.html FEATURES Single +3.3V ±0.3V power supply Industry-standard x16 pinout, timing, functions, and packages 12 row, 10 column addresses High-performance CMOS silicon-gate process All inputs, outputs and clocks are LVTTL-compatible FAST PAGE MODE (FPM) access 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms PIN ASSIGNMENT (Top View) 50-Pin TSOP VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC VCC WE# RAS# NC NC NC NC A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC VSS CASL# CASH# OE# NC NC NC A11 A10 A9 A8 A7 A6 VSS OPTIONS Plastic Package 50-pin TSOP (400 mil) Timing 50ns access 60ns access Refresh Rate Standard Refresh Part Number Example MARKING TG -5 -6 None MT4LC4M16F5TG-5 KEY TIMING PARAMETERS SPEED -5 -6 tRC 90ns 110ns tRAC 50ns 60ns tPC 30ns 35ns tAA 25ns 30ns tCAC 13ns 15ns NOTE: 1. The # symbol indicates signal is active LOW. GENERAL DESCRIPTION The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits organized in a x16 configuration. The MT4LC4M16F5 is functionally organized as 4,194,304 locations containing 16 bits each. The 4,194,304 memory locations are arranged in 4,09...