MT7620

MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip MT7620 Overview The MT7620 SoC includes a high performance 580 MHz MIPS24KEc CPU core and USB host controller/PHY, which is designed to enable a multitude of high performance, cost-effective IEEE 802.11n applications with a MediaTek (Ralink) client card. Functional Block Diagram EJTAG 16-Bit SDR/DDR1/DDR2 MIPS 24KEc 64 KB I-Cache 32 KB DCache (580 MHz) OCP _IF OCP Bridge DRAM Controller Arbiter RBUS (SYS_CLK) SDHC SD Single-Port USB 2.0 PHY Host/ Device PBUS PCIe 1.1 PHY WLAN 11n 2x2 Switch (4FE + 2GE) GDMA PCIe x1 2.4 GHz 5-Port EPHY RJ45 x5 RGMII TMII/MII x2 Figure 1-1 MT7620 Block Diagram PBUS To CPU interrupt s INTC Timer SPI NFC UART GPIO I2C I2S PCM x4 SPI NAND UART GPIO /LED I2C I2S PCM There are several masters (MIPS 24KEc, USB , PCI Express) in the MT7620 SoC on a high performance, low latency Rbus, (Ralink Bus). In addition, the MT7620 SoC supports lower speed peripherals such as UART, GPIO, and SPI via a low speed peripheral bus (Pbus). The SDRAM/DDR1/DDR2 controller is the only bus slave on the Rbus. It includes an Advanced Memory Scheduler to arbitrate the requests from bus masters, enhancing the performance of memory access intensive tasks. PGMT7620_V.1.0_040503 Page 2 of 523 MT7620 PROGRAMMING GUIDE Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip...