MX98728EC

MX98728EC GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION 1.6KB TX FIFO to support maximum network throughput in the full duplex mode 16/8 bits SRAM interface of the packet buffer supporting burst DMA for on-chip FIFOs Flexible packet buffer partition and addressing space for up to 1MB NWAY autonegotiation function to automatically set up network speed and protocol 3 loop back modes for system level diagnosis Supports 64 bits hash table for multicast addressing, broadcast control. Optional EEPROM configuration, supports 1K bits and 4K bits EEPROM interface Supports software EEPROM interface for easy upgrade of EEPROM contents 5V CMOS in an 160 PQFP package 1.0 Features 32 bits general purpose asynchronous bus architecture up to 33Mhz for easy system application Single chip solution integrating 10/100 TP transceiver to reduce overall cost Optional MII interface for external tranceiver. Fully compliant with the IEEE 802.3u spec. Supports 32/16 bits x1, x2, x4 burst read transfers for the receive packet buffer Packet buffer access through an IO mapped port or host DMA for a wide variety of bus applications Programmable bus integrity check timer and interrupt assertion scheme Supports 16/8 bits packet buffer data width and 32/ 16 bits host bus data width Separated TX and RX FIFOs to support the full duplex mode, independent TX and RX channel Rich on-chip registers to support a wide variety of network management func...