N87C251SP

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER J Real Time and Programmed Wait State Bus Operation Binary-code Compatible with MCS® 51 J J J w w J a D . w Pin Compatible with 44-lead PLCC and 40-lead PDIP MCS 51 Sockets Register-based MCS 251 Architecture — 40-byte Register File — Registers Accessible as Bytes, Words, and Double Words Enriched MCS 51 Instruction Set — 16-bit and 32-bit Arithmetic and Logic Instructions — Compare and Conditional Jump Instructions — Expanded Set of Move Instructions Linear Addressing 256-Kbyte Expanded External Code/Data Memory Space ROM/OTPROM/EPROM Options: 16 Kbytes (SB/SQ), 8 Kbytes (SA/SP), or without ROM/OTPROM/EPROM 16-bit Internal Code Fetch 64-Kbyte Extended Stack Space On-chip Data RAM Options: 1-Kbyte (SA/SB) or 512-Byte (SP/SQ) 8-bit, “Min” 2-clock External Code Fetch in Page Mode ® S a t e e h U 4 t m o .c Commercial/Express J User-selectable Configurations: — External Wait States (0-3 wait states) — Address Range & Memory Mapping — Page Mode 32 Programmable I/O Lines Seven Maskable Interrupt Sources with Four Programmable Priority Levels Hardware Watchdog Timer Programmable Counter Array — High-speed Output — Compare/Capture Operation — Pulse Width Modulator — Watchdog Timer Programmable Serial I/O Port — Framing Error Detection — Automatic Address Recognition High-performance CHMOS Technology Static Standby to 16-MHz Operation J J J J J Three Flexible 16-bit Timer/counters J J J J J J J This documen...