NDP6030L

June 1996 NDP6030L / NDB6030L N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as DC/DC converters and high efficiency switching circuits where fast switching, low in-line power loss, and resistance to transients are needed. Features 52 A, 30 V. RDS(ON) = 0.0135 Ω @ VGS=10 V RDS(ON) = 0.020 Ω @ VGS=4.5 V. Critical DC electrical parameters specified at elevated temperature. Rugged internal source-drain diode can eliminate the need for an external Zener diode transient suppressor. High density cell design for extremely low RDS(ON). 175°C maximum junction temperature rating. _______________________________________________________________________________ D G S Absolute Maximum Ratings Symbol VDSS VGSS ID Parameter Drain-Source Voltage T C = 25°C unless otherwise noted NDP6030L 30 ± 16 52 156 75 0.5 -65 to 175 275 NDB6030L Units V V A Gate-Source Voltage - Continuous Drain Current - Continuous - Pulsed PD Total Power Dissipation @ TC = 25°C Derate above 25°C W W/°C °C °C TJ,TSTG TL Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds Thermal Resistance, Junct...