NDT455N

July 1996 NDT455N N-Channel Enhancement Mode Field Effect Transistor General Description These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as DC motor control and DC/DC conversion where fast switching, low in-line power loss, and resistance to transients are needed. Features 11.5 A, 30 V. RDS(ON) = 0.015 Ω @ VGS = 10 V RDS(ON) = 0.02 Ω @ VGS = 4.5 V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package. ________________________________________________________________________________ D D G D S G S Absolute Maximum Ratings Symbol VDSS VGSS ID Parameter Drain-Source Voltage Gate-Source Voltage Drain Current T A = 25°C unless otherwise noted NDT455N 30 20 (Note 1a) Units V V A - Continuous - Pulsed ± 11.5 ± 40 PD Maximum Power Dissipation (Note 1a) (Note 1b) (Note 1c) 3 1.3 1.1 -65 to 150 W TJ,TSTG Operating and Storage Temperature Range °C THERMAL CHARACTERISTICS RθJA RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1a) (Note 1) 42 12 °C/W °C/W © 1997 Fairchild S...