DatasheetsPDF.com

NTE74LS75 Datasheet

Part Number NTE74LS75
Manufacturers NTE
Logo NTE
Description 4-Bit Bistable Latch
Datasheet NTE74LS75 DatasheetNTE74LS75 Datasheet (PDF)

NTE74LS75 Integrated Circuit TTL − 4−Bit Bistable Latch Description: The NTE74LS75 is a 4−bit bistable latch in a 16−Lead plastic DIP type package that is ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable (C) is high and the Q output will follow the data input as long as the enable remains high. When the enable goes low, the inform.

  NTE74LS75   NTE74LS75






Part Number NTE74LS78
Manufacturers NTE
Logo NTE
Description Dual J-K Flip-Flop
Datasheet NTE74LS75 DatasheetNTE74LS78 Datasheet (PDF)

NTE74LS78 Integrated Circuit TTL − Dual J−K Flip−Flop with Preset, Common Clock and Common Clear Description: The NTE74LS78 is a dual J−K flip−flop in a 14−Lead plastic DIP type package that contains two negative−edge−triggered flip−flops with individual J−K, preset inputs, and common clock and common clear inputs. The logic levels at the J and K inputs may be allowed to change while the clock pulse is high and the flip−flop will perform according to the function table as long as minimum setup .

  NTE74LS75   NTE74LS75







Part Number NTE74LS76A
Manufacturers NTE
Logo NTE
Description Dual J-K Flip-Flop
Datasheet NTE74LS75 DatasheetNTE74LS76A Datasheet (PDF)

NTE74LS76A Integrated Circuit TTL − Dual J−K Flip−Flop with Preset and Clear Description: The NTE74LS76A is a dual J−K flip−flop in a 16−Lead plastic DIP type package that contains two independent negative−edge−triggered flip−flops. The J and K inputs must be stable one setup time prior to the high−to−low clock transitions for predictable operation. The preset and clear are asynchronous active low inputs. When low they override the clock and data inputs forcing the outputs to the steady state l.

  NTE74LS75   NTE74LS75







Part Number NTE74LS74A
Manufacturers NTE
Logo NTE
Description Dual D-Type Positive-Edge-Triggered Flip-Flop
Datasheet NTE74LS75 DatasheetNTE74LS74A Datasheet (PDF)

NTE74LS74A Integrated Circuit TTL, Dual D−Type Positive−Edge−Triggered Flip−Flop w/Preset and Clear Description: The NTE74LS74A contains two independent D−type positive−edge−triggered flip−flops in a 14−Lead DIP type package characterized for operating from 0 to +70C. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the D input meeting the setup time requirements are transferre.

  NTE74LS75   NTE74LS75







4-Bit Bistable Latch

NTE74LS75 Integrated Circuit TTL − 4−Bit Bistable Latch Description: The NTE74LS75 is a 4−bit bistable latch in a 16−Lead plastic DIP type package that is ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable (C) is high and the Q output will follow the data input as long as the enable remains high. When the enable goes low, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the enable is permitted to go high. The NTE74LS75 features complementary Q and Q outputs from a 4−bit latch and are completely compatible with all popular TTL families. All inputs are diode−clamped to minimize transmission−line effects and simplify system design. Absolute Maximum Ratings: (Note 1) Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65C to +150C Note 1. Voltag.


2019-11-15 : SN74AXC8T245    OPA2189    TSOP98540    TSOP98556    TSOP98538    ARE104HC90    ARE1006C90    BMI270    TSOP98536    TSOP98533   


@ 2014 :: Datasheetspdf.com ::
Semiconductors datasheet search & download site (Privacy Policy & Contact)