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NTE74LS78 Datasheet

Part Number NTE74LS78
Manufacturers NTE
Logo NTE
Description Dual J-K Flip-Flop
Datasheet NTE74LS78 DatasheetNTE74LS78 Datasheet (PDF)

NTE74LS78 Integrated Circuit TTL − Dual J−K Flip−Flop with Preset, Common Clock and Common Clear Description: The NTE74LS78 is a dual J−K flip−flop in a 14−Lead plastic DIP type package that contains two negative−edge−triggered flip−flops with individual J−K, preset inputs, and common clock and common clear inputs. The logic levels at the J and K inputs may be allowed to change while the clock pulse is high and the flip−flop will perform according to the function table as long as minimum setup .

  NTE74LS78   NTE74LS78






Part Number NTE74LS76A
Manufacturers NTE
Logo NTE
Description Dual J-K Flip-Flop
Datasheet NTE74LS78 DatasheetNTE74LS76A Datasheet (PDF)

NTE74LS76A Integrated Circuit TTL − Dual J−K Flip−Flop with Preset and Clear Description: The NTE74LS76A is a dual J−K flip−flop in a 16−Lead plastic DIP type package that contains two independent negative−edge−triggered flip−flops. The J and K inputs must be stable one setup time prior to the high−to−low clock transitions for predictable operation. The preset and clear are asynchronous active low inputs. When low they override the clock and data inputs forcing the outputs to the steady state l.

  NTE74LS78   NTE74LS78







Part Number NTE74LS75
Manufacturers NTE
Logo NTE
Description 4-Bit Bistable Latch
Datasheet NTE74LS78 DatasheetNTE74LS75 Datasheet (PDF)

NTE74LS75 Integrated Circuit TTL − 4−Bit Bistable Latch Description: The NTE74LS75 is a 4−bit bistable latch in a 16−Lead plastic DIP type package that is ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable (C) is high and the Q output will follow the data input as long as the enable remains high. When the enable goes low, the inform.

  NTE74LS78   NTE74LS78







Part Number NTE74LS74A
Manufacturers NTE
Logo NTE
Description Dual D-Type Positive-Edge-Triggered Flip-Flop
Datasheet NTE74LS78 DatasheetNTE74LS74A Datasheet (PDF)

NTE74LS74A Integrated Circuit TTL, Dual D−Type Positive−Edge−Triggered Flip−Flop w/Preset and Clear Description: The NTE74LS74A contains two independent D−type positive−edge−triggered flip−flops in a 14−Lead DIP type package characterized for operating from 0 to +70C. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the D input meeting the setup time requirements are transferre.

  NTE74LS78   NTE74LS78







Dual J-K Flip-Flop

NTE74LS78 Integrated Circuit TTL − Dual J−K Flip−Flop with Preset, Common Clock and Common Clear Description: The NTE74LS78 is a dual J−K flip−flop in a 14−Lead plastic DIP type package that contains two negative−edge−triggered flip−flops with individual J−K, preset inputs, and common clock and common clear inputs. The logic levels at the J and K inputs may be allowed to change while the clock pulse is high and the flip−flop will perform according to the function table as long as minimum setup and hold times are observed. The preset and clear are asynchronous active low inputs. When low they override the clock and data inputs forcing the outputs to the steady state levels as shown in the function table. Absolute Maximum Ratings: (Note 1) Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65C to +150C Note 1. Voltage values are with respect to network ground terminal. Recommended Operating Conditions: Parameter Supply Voltage High−Level Input Voltage Low−Level Input Voltage .


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