2'&6;([[
®
$0,+* PLFURQ &026 *DWH $UUD\
Description
ODCSXExx is a family of 4 to 16 mA, non-inverting, CMOS-level...
2'&6;([[
®
$0,+* PLFURQ &026 *DWH $UUD\
Description
ODCSXExx is a family of 4 to 16 mA, non-inverting,
CMOS-level, tristate output buffer pieces with active low enables and controlled slew rate outputs.
Logic Symbol
Truth Table
ODCSXExx EN
SL
A
PADM
EN A PADM
LL
L
LH
H
HX
Z
HDL Syntax Verilog .................... ODCSXExx inst_name (PADM, A, EN); VHDL...................... inst_name: ODCSXExx port map (PADM, A, EN);
Pin Loading
Pin Name
A (eq-load) EN (eq-load) PADM (pF)
ODCSXE04 2.3 6.9 4.94
Power Characteristics
Cell Output Drive (mA)
ODCSXE04
4
ODCSXE08
8
ODCSXE12
12
ODCSXE16
16
a. See page 2-15 for power equation.
ODCSXE08 2.3 6.9 4.94
Load
ODCSXE12 2.3 6.9 4.94
ODCSXE16 2.3 6.9 4.94
Power Characteristicsa
Static IDD (TJ = 85°C) (nA) TBD
EQLpd (Eq-load) 218.9
TBD
240.3
TBD
261.1
TBD
283.9
Pad Logic
4-17
2'&6;([[
®
$0,+* PLFURQ &026 *DWH $UUD\
Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Capac...
