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P24C32E Datasheet

Part Number P24C32E
Manufacturers Puya
Logo Puya
Description I2C-Compatible Serial E2PROM
Datasheet P24C32E DatasheetP24C32E Datasheet (PDF)

P24C32E I2C-Compatible Serial E2PROM Data Sheet Rev.1.0 General Description The P24C32E is 32-Kbit I2C-compatible Serial EEPROM (Electrically Erasable Programmable Memory) device. It contains a memory array of 4096×8bits, which is 32 bytes per page. Features  Single Supply Voltage and High Speed  Minimum operating voltage down to 1.7V  1 MHz clock from 1.7V to 5.5V  Low power CMOS technology  Read current 100uA, maximum  Write current 0.5mA, maximum  Schmitt Trigger, Filtered Inpu.

  P24C32E   P24C32E






Part Number P24C32D
Manufacturers Puya
Logo Puya
Description I2C-Compatible Serial E2PROM
Datasheet P24C32E DatasheetP24C32D Datasheet (PDF)

P24C32D I2C-Compatible Serial E2PROM Data Sheet Rev.1.0 General Description The P24C32D is 32-KbitI2C-compatibleSerial EEPROM (Electrically Erasable Programmable Memory) device. It contains a memory array of 4096× 8bits, which is32-byteper page. P24C32D provides the following devices for different application. Device Selection Table Device Name P24C32D-MI Note 1: 400 kHz for VCC< 2.5V. Suppy 1.7V~5.5V Temp. Range -40°C ~ 85°C Features  Single Supply Voltage and High Speed  Minimum opera.

  P24C32E   P24C32E







I2C-Compatible Serial E2PROM

P24C32E I2C-Compatible Serial E2PROM Data Sheet Rev.1.0 General Description The P24C32E is 32-Kbit I2C-compatible Serial EEPROM (Electrically Erasable Programmable Memory) device. It contains a memory array of 4096×8bits, which is 32 bytes per page. Features  Single Supply Voltage and High Speed  Minimum operating voltage down to 1.7V  1 MHz clock from 1.7V to 5.5V  Low power CMOS technology  Read current 100uA, maximum  Write current 0.5mA, maximum  Schmitt Trigger, Filtered Inputs for Noise Suppression  Sequential & Random Read Features  Page Write Modes, Partial Page Writes Allowed  Software Write Protection(SWP) for Programmable Block  Upper quarter memory array  Upper half memory array  Upper 3/4 memory array  Whole memory array  Software Programmable Device ID Configuration  3 BIT DSC Register and configured by DSCWR command  Locked forever if Lock ID Page command executed  Additional Write Lockable Page an.


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