P2V28S20DTP-7

128Mb Synchronous DRAM P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT) 128Mb SDRAM Specification P2V28S20DTP-7,-75,-8 P2V28S30DTP-7,-75,-8 P2V28S40DTP-7,-75,-8 MIRA TECHNOLOGY INC. 8F., 68, SEC.3, NANKING E. RD. , TAIPEI, TAIWAN, R.O.C. TEL:886-2-25170055.25170066 FAX:886-2-25174575 JULY.2000 Rev.2.2 128Mb Synchronous DRAM 128Mb Synchronous DRAM P2V28S20ATP-7,-75,-8 P2V28S30ATP-7,-75,-8 P2V28S40ATP-7,-75,-8 PRELIMINARY (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT) Some of contents are described for general products and are subject to change without notice. DESCRIPTION P2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and P2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and P2V28S40ATP is organized as 4-bank x 2,097, 152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK. P2V28S20ATP,P2V28S30ATP and P2V28S40ATP achieve very high speed data rates up to 166MHz, and are suitable for main memories or graphic memories in computer systems. FEATURES ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time (Min.) CL=2 CL=3 -7 7ns 45ns CL=2 CL=3 V28S20D 20ns 5.4...