FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times) – 10/12/15/20/25/35/45 ns (Commercial) – 1...
FEATURES
Full
CMOS, 6T Cell
High Speed (Equal Access and Cycle Times) – 10/12/15/20/25/35/45 ns (Commercial) – 12/15/20/25/35 /45 ns (Industrial) – 15/20/25/35/45/55/70/85 ns (Military)
Low Power Operation
Single 5V±10% Power Supply
Data Retention with 2.0V Supply (P4C187L)
Separate Data I/O
P4C187/P4C187L
ULTRA HIGH SPEED 64K x 1 STATIC
CMOS RAMS
Three-State Output TTL Compatible Output Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved) – 22-Pin 300 mil DIP – 24-Pin 300 mil SOJ – 22-Pin 290x490 mil LCC – 28-Pin 350x550 mil LCC
DESCRIPTION
The P4C187/P4C187Lare 65, 536-bit ultra high speed static RAMs organized as 64K x 1. The
CMOS memories require no clocks or refreshing and have equal access and cycle times. The RAMs operate from a single 5V ± 10% tolerance power supply. Data integrity is maintained for supply
voltages down to 2.0V for the Low Power version, typically drawing 10µA.
Access times as fast as 10 nanoseconds a...
