flash microcontroller. P89C662 Datasheet

P89C662 Datasheet PDF

Part Number



8-bit 80C51 5V low power 16 kB/32 kB/64 kB flash microcontroller



Total Page 30 Pages
Download P89C662 Datasheet

8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash
microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
Rev. 3.1 — 17 October 2011
Product data sheet
1. General description
The P89V660/662/664 are 80C51 microcontrollers with 16 kB/32 kB/64 kB flash and
512 B/1 kB/2 kB of data RAM. These devices are designed to be drop-in and software
compatible replacements for the P89C660/662/664 devices. Both the In-System
Programming (ISP) and In-Application Programming (IAP) boot codes are upward
Additional features of the P89V660/662/664 devices when compared to the
P89C660/662/664 devices are the inclusion of a secondary 100 kHz byte-wide I2C-bus
interface, an SPI interface, four addition I/O pins (Port 4), and the ability to erase code
memory in 128-byte pages.
The IAP capability combined with the 128-byte page size allows for efficient use of the
code memory for non-volatile data storage.
2. Features and benefits
2.1 Principal features
Dual 100 kHz byte-wide I2C-bus interfaces
128-byte page erase for efficient use of code memory as non-volatile data storage
0 MHz to 40 MHz operating frequency in 12x mode, 20 MHz in 6x mode
16 kB/32 kB/64 kB of on-chip flash user code memory with ISP and IAP
512 B/1 kB/2 kB RAM
SPI (Serial Peripheral Interface) and enhanced UART
PCA (Programmable Counter Array) with PWM and Capture/Compare functions
Three 16-bit timers/counters
Four 8-bit I/O ports, one 4-bit I/O port
WatchDog Timer (WDT)
2.2 Additional features
30 ms page erase, 150 ms block erase
Support for 6-clock (default) or 12-clock mode selection via ISP or parallel programmer
PLCC44 and TQFP44 packages
Ten interrupt sources with four priority levels
Second DPTR register
Low EMI mode (ALE inhibit)
Power-down mode with external interrupt wake-up

NXP Semiconductors
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
Idle mode
2.3 Comparison to the P89C660/662/664 devices
SPI interface. The P89V660/662/664 devices include an SPI interface that was not
present on the P89C660/662/664 devices.
Dual I2C-bus interfaces. The P89V660/662/664 devices have two I2C-bus interfaces.
The P89C660/662/664 devices have one.
More I/O pins. The P89V660/662/664 devices have an additional four-bit I/O port,
Port 4.
The 6x/12x mode on theP89V660/662/664 devices is programmable and erasable
using ISP and IAP as well as parallel programmer mode. The P89C660/662/664
devices could only be switched using parallel programmer mode.
Smaller block sizes. The smallest block size on the P89C660/662/664 devices was
8 kB. The P89V660/662/664 devices have a page size of 128 B. These small pages
can be erased and reprogrammed using IAP function calls making use of the code
memory for non-volatile data storage practical. Each page erase is 30 ms or less. The
IAP and ISP code in P89V660/662/664 devices support these 128-byte page
operations. In addition, the IAP and ISP code uses multiple page erase operations to
emulate the erasing of the larger block sizes (8 kB and 16 kB to maintain firmware
Status bit versus Status byte. The P89V660/662/664 devices used a Status byte to
control the automatic entry into ISP mode following a reset. On the P89V660/662/664
devices this has changed to a single Status bit. Since the ISP entry was based on the
zero/non-zero value of the Status byte this is an almost identical operation on the
P89V660/662/664 devices.
Faster block erase. The erase time for the entire user code memory of the
P89V660/662/664 devices is 150 ms.
3. Ordering information
Table 1. Ordering information
Type number
PLCC44 plastic leaded chip carrier; 44 leads
plastic thin quad flat package; 44 leads; body
10 10 1.0 mm
PLCC44 plastic leaded chip carrier; 44 leads
plastic thin quad flat package; 44 leads; body
10 10 1.0 mm
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.1 — 17 October 2011
© NXP B.V. 2011. All rights reserved.
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