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PL585-28 Datasheet

Part Number PL585-28
Manufacturers Micrel
Logo Micrel
Description 19MHz to 250MHz Low Phase-Noise VCXO
Datasheet PL585-28 DatasheetPL585-28 Datasheet (PDF)

(Preliminary) PL585-28 19MHz to 250MHz Low Phase-Noise VCXO FE AT UR E S  < 0.6ps RMS phase jitter (12kHz to 20MHz) at 155.52MHz  30ps max peak to peak period jitter  Ultra Low-Power Consumption  < 90mA @155MHz PECL output  <10A at Power Down (PDB) Mode  Input Frequency:  Fundamental Crystal: 19MHz to 40MHz  Output Frequency:  19MHz to 250MHz output.  Output type: LVPECL  High Linearity VCXO: <10% linearity  Pullability: ±150 ppm  Programmable OE input polarity selection.  Power.

  PL585-28   PL585-28






19MHz to 250MHz Low Phase-Noise VCXO

(Preliminary) PL585-28 19MHz to 250MHz Low Phase-Noise VCXO FE AT UR E S  < 0.6ps RMS phase jitter (12kHz to 20MHz) at 155.52MHz  30ps max peak to peak period jitter  Ultra Low-Power Consumption  < 90mA @155MHz PECL output  <10A at Power Down (PDB) Mode  Input Frequency:  Fundamental Crystal: 19MHz to 40MHz  Output Frequency:  19MHz to 250MHz output.  Output type: LVPECL  High Linearity VCXO: <10% linearity  Pullability: ±150 ppm  Programmable OE input polarity selection.  Power Supply: 3.3V, ±10%  Operating Temperature Ranges:  Commercial: 0C to 70C  Industrial: -40C to 85C  Available in Die or Wafer 88.6 mil XIN, FIN XOUT PIN CONFIGURATION 65 mil VCON/ 9 SCLK 8 Die ID OE/PDB/ SDIO DNC 10 11 GND_ANA GND_DIG GND_BUF 12 13 14 (0,0) PL585 (1650,2250) 7 6 VDD_ANA 5 VDD_DIG 4 VDD_BUF 3 QB 2 VDD_BUF 1Q DESCRIPTION The PL585-28 is a Dual LC core monolithic IC clock, capable of maintaining sub-picoseconds RMS phase jitter, while covering a wide frequency output range up to 250MHz, without the use of external components. The high performance and high frequency output is achieved using a low cost fundamental crystal of between 19MHz and 40 MHz. The PL585-28 is designed to address the demanding requirements of high performance applications such as Fiber Channel, serial ATA, Ethernet, SAN, SONET/SDH, etc. BLOCK DIAGRAM OE/PDB XIN/REF XOUT VCON (Default pre-programmed output path) Xtal Osc PD/CP LF – HF LCVCOs Varicap Programmable Function M D.


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