PR31500ABC

INTEGRATED CIRCUITS MIPS PR31500 Poseidon embedded processor Preliminary specification Version 0.1 1996 Sep 24 Philips Semiconductors Philips Semiconductors Preliminary specification Poseidon embedded processor Version 0.1 GENERAL DESCRIPTION PR31500 Processor is a single-chip, low-cost, integrated embedded processor consisting of MIPS R3000 core and system support logic to interface with various types of devices. PR31500 consists of a MIPS R3000 RISC CPU with 4 KBytes of instruction cache memory and 1 KByte of data cache memory, plus integrated functions for interfacing to numerous system components and external I/O modules. The R3000 RISC CPU is also augmented with a multiply/accumulate module to allow integrated DSP functions, such as a software modem for high-performance standard data and fax protocols. The PR31500 processor can support both Little and Big Endian operating systems. In addition the PR31500 provides a memory management unit with an on-chip Translation Look aside Buffer (TLB) for very fast virtual to physical address translation. PR31500 also contains multiple DMA channels and a high-performance and flexible Bus Interface Unit (BIU) for providing an efficient means for transferring data between external system memory, cache memory, the CPU core, and external I/O modules. The types of external memory devices supported include dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), static random access memory (SRAM), Flash m...