PSMN2R0-30YL

www.DataSheet4U.com PSMN2R0-30YL N-channel TrenchMOS logic level FET Rev. 01 — 10 September 2008 Preliminary data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in industrial and communications applications. 1.2 Features and benefits „ High efficiency due to low switching and conduction losses „ Suitable for logic level gate drive sources 1.3 Applications „ Class-D amplifiers „ DC-to-DC converters „ Motor control „ Server power supplies 1.4 Quick reference data Table 1. VDS ID Ptot Quick reference Conditions Tmb = 25 °C; VGS = 10 V; see Figure 1; see Figure 3; Tmb = 25 °C; see Figure 2 [1] Min Typ Max 30 100 97 Unit V A W drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C drain current total power dissipation gate-drain charge Symbol Parameter Dynamic characteristics QGD VGS = 4.5 V; ID = 10 A; VDS = 12 V; see Figure 14; see Figure 15 VGS = 10 V; ID = 15 A; Tj = 25 °C; see Figure 12 7.5 nC Static characteristics RDSon drain-source on-state resistance 1.56 2 mΩ [1] Continuous current is limited by package. www.DataSheet4U.com NXP Semiconductors PSMN2R0-30YL N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pin 1 2 3 4 mb S S S G D Pinning information Symbol Description source source source gate mounting base; connected to drain mbb076 Simplified outline mb Graphic symbol D G S 1 2 3 4...