adapter. PTN3393 Datasheet

PTN3393 Datasheet PDF

Part PTN3393
Description 2-lane DisplayPort to VGA adapter
Feature PTN3393 2-lane DisplayPort to VGA adapter IC Rev. 4 — 10 June 2014 Product data sheet 1. General d.
Manufacture NXP
Download PTN3393 Datasheet

PTN3393 2-lane DisplayPort to VGA adapter IC Rev. 4 — 10 Jun PTN3393 Datasheet

2-lane DisplayPort to VGA adapter IC
Rev. 4 — 10 June 2014
Product data sheet
1. General description
The PTN3393 is a DisplayPort to VGA adapter IC designed to connect a DisplayPort
source to a VGA sink. The PTN3393 integrates a DisplayPort receiver and a high-speed
triple video digital-to-analog converter that supports display resolutions from VGA to
WUXGA (see Table 5). The PTN3393 supports either one or two DisplayPort v1.1a lanes
operating at either 2.7 Gbit/s or 1.62 Gbit/s per lane. The PTN3393 has ‘Flash-over-AUX’
capability enabling simple firmware upgradability in the field.
The PTN3393 supports I2C-bus over AUX per DisplayPort v1.1a specification (Ref. 1),
and bridges the VESA DDC channel to the DisplayPort Interface.
The PTN3393 is designed for single supply and minimizes application costs. It can be
powered directly from the DisplayPort source side 3.3 V supply without a need for
additional core voltage regulator. The VGA output is powered down when there is no valid
DisplayPort source data being transmitted. The PTN3393 also aids in monitor detection
by performing load sensing and reporting sink connection status to the source.
2. Features and benefits
2.1 VESA-compliant DisplayPort v1.1a converter
Main Link: 1-lane and 2-lane modes supported
HBR (High Bit Rate) at 2.7 Gbit/s per lane
RBR (Reduced Bit Rate) at 1.62 Gbit/s per lane
BER (Bit Error Rate) better than 109
Down-spreading SSC (Spread Spectrum Clocking) supported
1 MHz AUX channel
Supports native AUX CH syntax
Supports I2C-bus over AUX CH syntax
Hot Plug Detect (HPD) signal to the source
Cost-effective design optimized for VGA application
2.2 DDC channel output
Supports 100 kbit/s I2C-bus speed, declared in DPCD register
Support of I2C-bus speed control by DisplayPort source via DPCD registers,
facilitating use of longer VGA cables
I2C Over Aux feature facilitates full support of MCCS, DDC-CI, and DDC protocols
(see Ref. 2)

NXP Semiconductors
2-lane DisplayPort to VGA adapter IC
2.3 Analog video output
VSIS 1.2 compliance (Ref. 3) for all supported video output modes
Analog RGB current-source outputs
VSYNC and HSYNC outputs
Pixel clock up to 240 MHz
Triple 8-bit Digital-to-Analog Converter (DAC)
Direct drive of double terminated 75 load with standard 700 mV (peak-to-peak)
2.4 General features
Supports ‘Flash-over-AUX’ field upgradability
Monitor presence detection. Connection/disconnection reported via HPD IRQ and
DPCD update.
All display resolutions from VGA to WUXGA are supported1, including e.g.:
WUXGA: 6 bits, 1920 1200, 60 Hz, 193 MHz pixel clock rate
WUXGA: 1920 1200, 60 Hz, reduced blanking, 154 MHz pixel clock rate
UXGA: 1600 1200, 60 Hz, 162 MHz pixel clock rate
SXGA: 1280 1024, 60 Hz, 108 MHz pixel clock rate
XGA: 1024 768, 60 Hz, 65 MHz pixel clock rate
SVGA: 800 600, 60 Hz, 40 MHz pixel clock rate
VGA: 640 480, 60 Hz, 25 MHz pixel clock rate
Any resolution and refresh rates are supported up to 8 bit color
Bits per color (bpc) supported1
6, 8 bits supported
10, 12, 16 bits supported by truncation to 8 MSBs
All VGA colorimetry formats (RGB) supported
Power modes
Active-mode power consumption:
~600 mW at UXGA / 162 MHz pixel clock
~500 mW at SXGA / 108 MHz pixel clock
~40 mW at Low-power mode or before link training started
On-board crystal oscillator for use with external 27 MHz crystal
ESD protection: 7 kV ESD HBM JEDEC
3.3 V 10 % power supply
Commercial temperature range: 0 C to 85 C
40-pin HVQFN, 6 mm 6 mm 0.85 mm (nominal); 0.5 mm pitch; lead-free package
1. Except for color depth beyond 8 bits, display resolutions and refresh rates are only limited to those which a standard 2-lane
DisplayPort configuration is able to support.
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 10 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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