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S6E1B36F0A Datasheet

Part Number S6E1B36F0A
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description Microcontroller
Datasheet S6E1B36F0A DatasheetS6E1B36F0A Datasheet (PDF)

PRELIMINARY S6E1B3 Series 32-bit ARM® Cortex®-M0+ FM0+ Microcontroller The S6E1B3 Series is a series of highly integrated 32-bit microcontrollers designed for embedded controllers aiming at low power consumption and low cost. This series has the ARM Cortex-M0+ Processor with on-chip Flash memory and SRAM, and consists of peripheral functions such as various timers, ADC and communication interfaces (UART, CSIO (SPI), I2C, I2S, Smart Card, and USB). The products which are described in this data .

  S6E1B36F0A   S6E1B36F0A






Microcontroller

PRELIMINARY S6E1B3 Series 32-bit ARM® Cortex®-M0+ FM0+ Microcontroller The S6E1B3 Series is a series of highly integrated 32-bit microcontrollers designed for embedded controllers aiming at low power consumption and low cost. This series has the ARM Cortex-M0+ Processor with on-chip Flash memory and SRAM, and consists of peripheral functions such as various timers, ADC and communication interfaces (UART, CSIO (SPI), I2C, I2S, Smart Card, and USB). The products which are described in this data sheet are placed into TYPE2-M0+ product categories in "FM0+ Family Peripheral Manual". Features 32-bit ARM Cortex-M0+ Core Processor version: r0p1 Maximum operating frequency: 40.8 MHz Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 24 peripheral interrupt with 4 selectable interrupt priority levels 24-bit System timer (Sys Tick): System timer for OS task management Bit Band Operation Compatible with Cortex-M3 bit band operation. On-Chip Memory Flash memory  Up to 512 K+48 Kbytes  Dual bank  upper bank : 512 Kbytes(64 Kbytes x 8) • lower bank : 48 Kbytes(8K bytes x 6)  Read cycle: 0 wait-cycle  Security function for code protection SRAM The on-chip SRAM of this series has one independent SRAM .  Up to SRAM: 60 K+4 Kbytes  4Kbytes: can retain value in Deep standby Mode USB Interface USB interface is composed of Device and Host PLL for USB is built-in, USB clock can be generated by multiplication of Main clock. USB Device  USB 2.0 Full-Spee.


2016-07-04 : BAS40W-06    2SK1679    2SK1678    2SK1677    2SK1676    2SK1675    2SK1674    2SK1667    2SK1667    2SK1662   


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