Camera Processor. SAA8122A Datasheet

SAA8122A Datasheet PDF

Part Number



Digital Still Camera Processor



Total Page 26 Pages
Download SAA8122A Datasheet

Digital Still Camera Processor (ImagIC family)
Rev. 01 — 20 April 2000
Objective specification
1. Description
The DSC SAA8122A is a high performance, low power, single-chip Million
Instructions Per Second (MIPS) based signal processor, part of the ImagIC family,
which is dedicated to image processing, compression, formatting and storage. The
DSC SAA8122A is optimized for use with Philips range of CCDs (e.g: FXA1022,
2 Mpixels CCD), V-driver (TDA9991), CDS/PGA/ADC (TDA9952), allowing easy
implementation of a complete system solution and fast development of high
performance consumer digital still cameras.
The SAA8122A is designed as a single-chip device, able to perform all treatments
and connections required for a wide range of Digital Still Cameras. Its embedded
RISC CPU, for which the development environment is available, enables shorter
development and validation cycles, as well as faster feature upgrade. Since one of
the main objectives of the SAA8122A is addressing a wide range of CCD sensors, a
DSP (with advanced embedded algorithm) for camera signal processing is integrated
with a high level of programmability for pulses generation.
The JPEG core is hardware based in order to allow high-speed image data
2. Featuresc
2.1 General
s Supports a wide range of progressive CCDs (VGA, SVGA, QGA, XGA, EQGA),
with RGB Bayer filters up to 2 Mpixels
s Performs an advanced RGB to YUV conversion
s Includes a smart measurement unit to speed up the control loop (focus, auto white
balance, etc.)
s Supports a wide range of LCD and TV formats (both NTSC and PAL) with text
insertion features
s Includes an embedded JPEG encoder/decoder unit
s Includes a MIPS PR3001 CPU, running at a frequency in a range from
12 to 28 MHz
s PRISC compatible PI-bus architecture, interrupt, power management, clock and
reset architectures
s Includes a dedicated video bus supporting SDRAM memory for picture storage

Philips Semiconductors
Digital Still Camera Processor (ImagIC family)
s Interface to ROM, DRAM, SRAM, flash and PC Card [Compact Flash and SSFDC
s Integrated general purpose peripheral units like a UART, timers, an I2C-bus
transceiver, ADC converters, RTC and I/O ports
s Includes USB and RS-232C communication interfaces.
2.2 External interfaces
s Two UART (RS-232) data ports with DMA capabilities (187.5 kbit/s) including
hardware flow control RxD, TxD, RTS, CTS for modem support
s 32 general purpose, bidirectional I/O interface pins, the first 8 bits may also be
used as interrupt inputs
s Two PWM outputs (8-bit resolution).
2.3 CPU related features
s 32-bit PR3001 core
s 1-kbyte data cache and 4-kbyte instruction cache
s Programmable low-power mode, including wake-up on interrupt
s Memory management unit [Translation Lookaside Buffer (TLB)]
s Two built in 24-bit general purpose timers and one 24-bit watchdog timer
s Real-time clock unit (active in sleep mode)
s On-chip 8-kbyte SRAM for storing code which needs fast execution
s Platform software based on real-time pSOS (plug-in Silicon Operating System).
2.4 DSP features
s Advanced colour reconstruction
s Programmable digital filters for noise reduction and contour enhancement
s 16 programmable measurement windows allowing to perform the measurements
necessary for exposure, white balance and focus adjustment in a DSC system;
available measurement outputs for exposure, white balance and focus control.
2.5 Pulse pattern generator features
s Programmable through dedicated PC-software, allowing to drive all CCDs
currently present in the market, as well as CDS/AGC/ADC chips: up to
8 × 8 kpixels.
2.6 JPEG
s Fully ISO10918 compliant
s Supports Tiff, Exif 2.1, DCF & DPOF
s Quick compression (4 images/s for a 1.3 Mpixels resolution).
2.7 USB interface
s Fully compatible with USB.
9397 750 07048
Objective specification
Rev. 01 — 20 April 2000
© Philips Electronics N.V. 2000. All rights reserved.
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