SJA2020

www.DataSheet4U.com SJA2020 ARM7 microcontroller with CAN and LIN controllers Rev. 01 — 5 April 2006 Objective data sheet 1. Introduction 1.1 About this document This document lists detailed information about the SJA2020 device. It focuses on factual information like pin information, register views, characteristics etc. Short descriptions are used to outline the concept of the features and functions. More details and background on developing applications for this device is given in the SJA2020 User manual (see Ref. 1). No explicit references are made to the User manual. Please refer to the SJA2020 Application note ‘Known issues’ (see Ref. 2) for corrections and additional product information. 1.2 Intended audience This document is written for engineers evaluating and/or developing systems, hard- and/or software for the SJA2020. Some basic knowledge of ARM processors and architecture and ARM7 in particular is assumed (see Ref. 3). 2. General description 2.1 Architectural overview The SJA2020 consists of an ARM7TDMI-S processor with real-time emulation support, the AMBA Advanced High-performance Bus (AHB) for interface to the on-chip memory controllers, a DTL bus (a universal Philips interface) for interface to the interrupt controller and three VLSI Peripheral Buses (VPB - a compatible superset of ARMs AMBA advanced peripheral bus) for connection to the on-chip peripherals clustered in so-called subsystems. The SJA2020 configures the ARM7TDMI-S processor in little endian by...