SM320C6201B

SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS D Highest Performance Fixed-Point Digital Signal Processor (DSP) SM320C6201 -- 6.67-ns Instruction Cycle Time -- 150-MHz Clock Rate -- Eight 32-Bit Instructions/Cycle -- 1200 MIPS D Highest Performance Fixed-Point Digital Signal Processor (DSP) SMJ320C6201B -- 6.67-ns Instruction Cycle Time -- 150-MHz Clock Rate -- Eight 32-Bit Instructions/Cycle -- 1200 MIPS D VelociTI™ Advanced Very Long Instruction Word (VLIW) ’C6200 CPU Core -- Eight Independent Functional Units: -- Six ALUs (32-/40-Bit) -- Two 16-Bit Multipliers (32-Bit Results) -- Load-Store Architecture With 32 32-Bit General-Purpose Registers -- Instruction Packing Reduces Code Size -- All Instructions Conditional D Instruction Set Features -- Byte-Addressable (8-, 16-, 32-Bit Data) -- 32-Bit Address Range -- 8-Bit Overflow Protection -- Saturation -- Bit-Field Extract, Set, Clear -- Bit-Counting -- Normalization D 1M-Bit On-Chip SRAM -- 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) -- 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as a Single Block (’6201) -- 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as Two Blocks for Improved Concurrency (’6201B) D 32-Bit External Memory Interface (EMIF) -- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM -- Glueless Interface to Asynchronous Memories: SRAM and EPROM D Four-Channel Bootloading Direct-Memory-Access (DMA) Controller with an Auxiliary Channel SGUS028A -- NOVEMBER 1998 ...