SM320C6424-EP

www.ti.com 1 Introduction 1.1 Features High-Performance Digital Signal Processor (C6424) – 2.5-, 2-, 1.67-, 1.43-ns Instruction Cycle Time – 400-, 500-, 600-, 700-MHz C64x+™ Clock Rate – Eight 32-Bit C64x+ Instructions/Cycle – 3200, 4000, 4800, 5600 MIPS – Fully Software-Compatible With C64x – Commercial and Automotive (Q or S suffix) Grades – Low-Power Device (L suffix) VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) SM320C64x+™ DSP Core – Eight Highly Independent Functional Units With VelociTI.2 Extensions: Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle – Load-Store Architecture With Non-Aligned Support – 64 32-Bit General-Purpose Registers – Instruction Packing Reduces Code Size – All Instructions Conditional – Additional C64x+™ Enhancements Protected Mode Operation Exceptions Support for Error Detection and Program Redirection Hardware Support for Modulo Loop Auto-Focus Module Operation C64x+ Instruction Set Features – Byte-Addressable (8-/16-/32-/64-Bit Data) – 8-Bit Overflow Protection – Bit-Field Extract, Set, Clear – Normalization, Saturation, Bit-Counting – VelociTI.2 Increased Orthogonality – C64x+ Extensions Compact 16-bit Instructions Additional Instructions to Support Complex Multiplies SM320C6424-EP FIXED-PO...