SM320C6711D-EP

SM320C6711ĆEP, SM320C6711BĆEP, SM320C6711CĆEP, SM320C6711DĆEP FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS D Controlled Baseline − One Assembly/Test Site, One Fabrication Site D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product-Change Notification D Qualification Pedigree† D Excellent-Price/Performance Floating-Point Digital Signal Processors (DSPs): 320C67x (C6711, C6711B, C6711C, and C6711D) − Eight 32-Bit Instructions/Cycle − 100-,150-,167-,200-,250-MHz Clock Rates − 10-, 6.7-, 6-, 5-, 4-ns Instruction Cycle Time − 600, 900, 1000, 1200, 1500 MFLOPS D Advanced Very Long Instruction Word (VLIW) C67x DSP Core − Eight Highly Independent Functional Units: − Four ALUs (Floating- and Fixed-Point) − Two ALUs (Fixed-Point) − Two Multipliers (Floating- and Fixed-Point) − Load-Store Architecture With 32 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional D Instruction Set Features − Hardware Support for IEEE Single-Precision and Double-Precision Instructions − Byte-Addressable (8-, 16-, 32-Bit Data) − 8-Bit Overflow Protection − Saturation − Bit-Field Extract, Set, Clear − Bit-Counting − Normalization D Device Configuration − Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot − Endianness: Little Endian, Big Endian SGUS054A − AUGUST 2004 − REVISED SEPTEMBER 2005 D L1/L2 Memory Architecture − 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped) − 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative) − 512K-Bit (64K-...