SM320DM642-HiRel

SM320DM642-HiRel www.ti.com SGUS063A – JUNE 2009 – REVISED OCTOBER 2010 SM320DM642-HiRel Video/Imaging Fixed Point Digital Signal Processor Check for Samples: SM320DM642-HiRel 1 SM320DM642-HiRel Video/Imaging Fixed-Point Digital Signal Processor 123 Controlled Baseline – Normalization, Saturation, Bit-Counting – One Assembly/Test/Fabrication Site – VelociTI.2™ Increased Orthogonality Enhanced Diminishing Manufacturing Sources L1/L2 Memory Architecture (DMS) Support – 128K Bit (16K Byte) L1P Program Cache Enhanced Product-Change Notification (Direct Mapped) Qualification Pedigree(1) High-Performance Digital Media Processor – 2 ns, 1.67 ns, 1.39 ns Instruction Cycle Time – 720 MHz Clock Rate (500/600 MHz devices are product preview only) – Eight 32-Bit Instructions/Cycle – 5760 MIPS – Fully Software-Compatible With C64x™ VelociTI.2™ Extensions to VelociTI™ Advanced Very Long Instruction Word (VLIW) TMS320C64x™ DSP Core – Eight Highly Independent Functional Units With VelociTI.2™ Extensions: Six ALUs (32/40 Bit), Each Supports Single 32 Bit, Dual 16 Bit, or Quad 8 Bit Arithmetic per Clock Cycle Two Multipliers Support Four 16 × 16-Bit Multiplies (32 Bit Results) per Clock Cycle or Eight 8 × 8 Bit Multiplies (16 Bit Results) per Clock Cycle – 128K Bit (16K Byte) L1D Data Cache (2-Way Set-Associative) – 2M Bit (256K Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) Endianess: Little Endian, Big Endian – 64 Bit External Memory Inte...