SM320F2812

SM320F2812, SMJ320F2812 Digital Signal Processors Data Manual Literature Number: SGUS053B December 2004 − Revised September 2006 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 1 Features Features D High-Performance Static CMOS Technology D Three 32-Bit CPU-Timers − 150 MHz (6.67-ns Cycle Time) − Low-Power (1.8-V Core at 135 MHz, 1.9-V Core at 150 MHz, 3.3-V I/O) Design − 3.3-V Flash Voltage D JTAG Boundary Scan Support† D High-Performance 32-Bit CPU D Motor Control Peripherals − Two Event Managers (EVA, EVB) − Compatible to 240xA Devices D Serial Port Peripherals − Serial Peripheral Interface (SPI) − Two Serial Communications Interfaces (TMS320C28x) (SCIs), Standard UART − 16 x 16 and 32 x 32 MAC Operations − Enhanced Controller Area Network − 16 x 16 Dual MAC (eCAN) − Harvard Bus Architecture − Multichannel Buffered Serial Port − Atomic Operations (McBSP) With SPI Mode − Fast Interrupt Response and Processing − Unified Memory Programming Model − 4M Linear Program Address Reach − 4M Linear Data Address Reach − Code-Efficient (in C/C++ and Assembly) − TMS320F24x/LF240x Processor Source Code Compatible D On-Chip Memory − Flash Devices: Up to 128K x 16 Flash (Four 8K x 16 and Six 16K x 16 Sectors) − ROM Devices: Up to 128K x 16 ROM − 1K x 16 OTP ROM − L0 and L1: 2 Blocks of 4K x 16 ...