SM55161A

VRAM Austin Semiconductor, Inc. 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM AVAILABLE AS MILITARY SPECIFICATIONS Military Processing Flow(SM Level) -55C to 125C temperature (Top View) 64-Pin Ceramic Flatpack (HKC) SM55161A Production PIN ASSIGNMENT FEATURES Organization: – DRAM: 262 144 by 16 Bits – SAM: 512 by 16 Bits Dual-Port Accessibility – Simultaneous and Asynchronous Access From the DRAM and SAM Ports Bidirectional Data-Transfer Function From the DRAM to the Serial-Data Register, and from Serial Data Register to DRAM (8 x 8) x 2 Block Write feature for fast area fill Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two Write-Per-Bit Modes to Simplify System Design Byte-Write Control (CASL, CASU) Provides Flexibility Extended Data Output for Faster System Cycle Time Enhanced Page-Mode Operation for Faster Access CAS-Before-RAS (CBR) and Hidden-Refresh Modes Long Refresh Period: Every 8 ms (Maximum) Up to 50-MHz Uninterrupted Serial-Data Streams 512 Selectable Serial-Register Starting Locations SE-Controlled Register-Status QSF Split-Register-Transfer Read for Simplified Real-Time Register Load Programmable Split-Register Stop Point 3-State Serial Outputs Allow Easy Multiplexing of Video-Data Streams Pin-out Compatible upgrade from SM55161 Compatible With JEDEC Standards PIN DESCRIPTIONS PIN A0-A8 CASL\, CASU\ DQ0-DQ15 DSF NC/GND DESCRIPTION Address inputs Column-Address Strobe/Byte Selects DRAM Data I/O, Write Mask Data ...