SN54ALS139

SN54ALS139, SN74ALS139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SDAS204A – APRIL 1982 – REVISED DECEMBER 1994 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporate Two Enable Inputs to Simplify Cascading and /or Data Reception Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs description The ′ALS139 are dual 2-line to 4-line decoders/demultiplexers designed for use in high-performance memory-decoding or datarouting applications requiring very short propagation delay times. In high-performance memory systems, these devices can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast-enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. Therefore, the effective system delay introduced by the Schottky-clamped system decoder is negligible. SN54ALS139 . . . J PACKAGE SN74ALS139 . . . D OR N PACKAGE (TOP VIEW) 1G 1 1A 2 1B 3 1Y0 4 1Y1 5 1Y2 6 1Y3 7 GND 8 16 VCC 15 2G 14 2A 13 2B 12 2Y0 11 2Y1 10 2Y2 9 2Y3 SN54ALS139 . . . FK PACKAGE (TOP VIEW) 2G VCC NC 1G 1A 3 2 1 20 19 1B 4 18 2A 1Y0 5 17 2B NC 6 16 NC 1Y1 7 15 2Y0 1Y2 8 14 2Y1 9 10 11 12 13 2Y2 2Y3 NC GND 1Y3 The ′ALS139 comprise two individual 2-line to 4-line decoders in a single package. The active-low enable (G) input can be...