HEX/QUADRUPLE D-TYPE FLIP-FLOP
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B HEX/QUADRUPLE D-TYPE FLIP-FL...
Description
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
D ’ALS174 and ’AS174 Contain Six Flip-Flops
With Single-Rail Outputs
D ’ALS175 and ’AS175B Contain Four
Flip-Flops With Double-Rail Outputs
D Buffered Clock and Direct-Clear Inputs
D Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
D Fully Buffered Outputs for Maximum
Isolation From External Disturbances
(’AS Only)
SN54ALS174 . . . J OR W PACKAGE SN54AS174 . . . J PACKAGE
SN74ALS174, SN74AS174 . . . D , N, OR NS PACKAGE (TOP VIEW)
SN54ALS175 . . . J OR W PACKAGE SN54AS175B . . . J PACKAGE
SN74ALS175, SN74AS175B . . . D, N, OR NS PACKAGE (TOP VIEW)
CLR 1 1Q 2 1D 3 2D 4 2Q 5 3D 6 3Q 7
GND 8
16 VCC 15 6Q 14 6D 13 5D 12 5Q 11 4D 10 4Q 9 CLK
CLR 1 1Q 2 1Q 3 1D 4 2D 5 2Q 6 2Q 7
GND 8
16 VCC 15 4Q 14 4Q 13 4D 12 3D 11 3Q 10 3Q 9 CLK
SN54ALS174, SN54AS174 . . . FK PACKAGE (TOP VIEW)
SN54ALS175 . . . FK PACKAGE (TOP VIEW)
1Q CLR NC VCC 4Q
1Q CLR NC VCC 6Q
3 2 1 20 19
1D 4
18 6D
2D 5
17 5D
NC 6
16 NC
2Q 7
15 5Q
3D 8
14 4D
9 10 11 12 13
3 2 1 20 19
1Q 4
18 4Q
1D 5
17 4D
NC 6
16 NC
2D 7
15 3D
2Q 8
14 3Q
9 10 11 12 13
2Q GND
NC CLK
3Q
3Q GND
NC CLK
4Q
NC – No internal connection
description
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR) input. The ’ALS175 an...
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