SN54ALS243A

SN54ALS243A, SN74ALS243A QUADRUPLE BUS TRANSCEIVERS WITH 3ĆSTATE OUTPUTS SDAS069B − DECEMBER 1982 − REVISED DECEMBER 1994 Two-Way Asynchronous Communication Between Data Buses pnp Inputs Reduce dc Loading Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs description These quadruple bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation allows for maximum flexibility in timing. These devices allow data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic levels at the output-enable (OEBA and OEAB) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated. The dual-enable configuration gives the quadruple bus transceivers the capability to store data by simultaneously enabling OEBA and OEAB. Each output reinforces its input in this transceiver configuration. When both control inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (eight in all) retain their states. The 4-bit codes appearing on the two sets of buses are identical. SN54ALS243A . . . J PACKAGE SN74ALS243A . . . D OR N PACKAGE (TOP VIEW) OEAB 1 NC 2 A1 3 A2 4 A3 5 A4 6 GND 7 14 VCC 13 OEBA 12 NC 11 B1 10 B2 9 B3 8 B4 SN54ALS243A . . . FK PACKAGE (TOP VIEW) NC OEAB NC VCC OEBA A1 3 2 ...