SN54ALS273

Contain Eight Flip-Flops With Single-Rail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs description These octal positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct-clear (CLR) input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input signal has no effect at the output. The SN54ALS273 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ALS273 is characterized for operation from 0°C to 70°C. 4Q GND CLK 5Q 5D SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SDAS218A – APRIL 1982 – REVISED DECEMBER 1994 SN54ALS273 . . . J PACKAGE SN74ALS273 . . . DW OR N PACKAGE (TOP VIEW) CLR 1 1Q 2 1D 3 2D 4 2Q 5 3Q 6 3D 7 4D 8 4Q 9 GND 10 20 VCC 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 CLK SN54ALS273 . . . FK PACKAGE (TOP VIEW) 1D 1Q CLR VCC 8Q 3 2 1 20 19 2D 4 18 8D 2Q 5 17 7D 3Q 6 16 7Q 3D 7 15 6...