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SN54LS13 Datasheet

SCHMITT TRIGGERS DUAL GATE/HEX INVERTER

SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The SN54LS/ 74LS13 and SN54LS / 74LS14 contain logic gates / inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Additionally, they have greater noise margin t.


Motorola Inc
SN54LS13.pdf

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Motorola Inc SN54LS13 Datasheet

SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The SN54LS/ 74LS13 and SN54LS / 74LS14 contain logic gates / inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Additionally, they have greater noise margin than conventional inverters. Each circuit contains a Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totem pole output. The Schmitt trigger uses positive feedback to effectively speed-up slow input transitions, and provide different input threshold voltages for positive and negative-going transitions. This hysteresis between the positive-going and negative-going input thresholds (typically 800 mV) is determined internally by resistor ratios and is essentially insensitive to temperature and supply voltage variations. LOGIC AND CONNECTION DIAGRAMS VCC 14 13 SN54 / 74LS13 12 11 10 9 8 SN54/74LS13 SN54/74.






SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The SN54LS/ 74LS13 and SN54LS / 74LS14 contain logic gates / inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Additionally, they have greater noise margin t.


Motorola Inc
SN54LS13J.pdf

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Motorola Inc SN54LS13J Datasheet

SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The SN54LS/ 74LS13 and SN54LS / 74LS14 contain logic gates / inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Additionally, they have greater noise margin than conventional inverters. Each circuit contains a Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totem pole output. The Schmitt trigger uses positive feedback to effectively speed-up slow input transitions, and provide different input threshold voltages for positive and negative-going transitions. This hysteresis between the positive-going and negative-going input thresholds (typically 800 mV) is determined internally by resistor ratios and is essentially insensitive to temperature and supply voltage variations. LOGIC AND CONNECTION DIAGRAMS VCC 14 13 SN54 / 74LS13 12 11 10 9 8 SN54/74LS13 SN54/74.






A PACKAGE OPTION ADDENDUM www.ti.com PACKAGING INFORMATION Orderable Device 76007012A Status Package Type Package Pins Package (1) Drawing Qty ACTIVE LCCC FK 20 1 Eco Plan (2) TBD 7600701EA 7600701FA 7700401EA 7700401FA JM38510/30702B2A JM38510/30702BEA JM38510/30702BFA JM38510/30702SEA JM38510/30702SFA M38510/30702B2A M38510/30702BEA.


Texas Instruments
SN54LS139A.pdf

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Texas Instruments SN54LS139A Datasheet

A PACKAGE OPTION ADDENDUM www.ti.com PACKAGING INFORMATION Orderable Device 76007012A Status Package Type Package Pins Package (1) Drawing Qty ACTIVE LCCC FK 20 1 Eco Plan (2) TBD 7600701EA 7600701FA 7700401EA 7700401FA JM38510/30702B2A JM38510/30702BEA JM38510/30702BFA JM38510/30702SEA JM38510/30702SFA M38510/30702B2A M38510/30702BEA M38510/30702BFA M38510/30702SEA M38510/30702SFA SN54LS139AJ SN54S139J ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE CDIP CFP CDIP CFP LCCC CDIP CFP CDIP CFP LCCC CDIP CFP CDIP CFP CDIP CDIP J 16 1 W 16 1 J 16 1 W 16 1 FK 20 1 J 16 1 W 16 1 J 16 25 W 16 1 FK 20 1 J 16 1 W 16 1 J 16 25 W 16 1 J 16 1 J 16 1 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Lead/Ball Finish (6) POST-PLATE A42 A42 A42 A42 POST-PLATE A42 A42 A42 A42 POST-PLATE A42 A42 A42 A42 A42 A42 24-Aug-2018 MSL Peak Temp (3) N / A for Pkg Type Op Temp (°C) -55 to 125 N / A.








 

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