SN54LS173A

SN54/74LS173A 4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS The SN54 / 74LS173A is a high-speed 4-Bit Register featuring 3-state outputs for use in bus-organized systems. The clock is fully edge-triggered allowing either a load from the D inputs or a hold (retain register contents) depending on the state of the Input Enable Lines (IE1, IE2). A HIGH on either Output Enable line (OE1, OE2) brings the output to a high impedance state without affecting the actual register contents. A HIGH on the Master Reset (MR) input resets the Register regardless of the state of the Clock (CP), the Output Enable (OE1, OE2) or the Input Enable (IE1, IE2) lines. Fully Edge-Triggered 3-State Outputs Gated Input and Output Enables Input Clamp Diodes Limit High-Speed Termination Effects 16 1 4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 MR 15 D0 14 D1 13 D2 12 D3 11 IE2 10 IE1 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 OE1 2 OE2 3 Q0 4 Q1 5 Q2 6 Q3 7 CP 8 GND 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC PIN NAMES LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 (7.5) U.L. D0 – D3 IE1 – IE2 OE1 – OE2 CP MR Q0 – Q3 Data Inputs Input Enable (Active LOW) Output Enable (Active LOW) Inputs Clock Pulse (Active HIGH ...