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SN54LS378 Datasheet

Part Number SN54LS378
Manufacturers Motorola
Logo Motorola
Description OCTAL D FLIP-FLOP
Datasheet SN54LS378 DatasheetSN54LS378 Datasheet (PDF)

OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 / 74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54 / 74LS378 is a 6-Bit Register with a buffered common enable. This device is similar to the SN54 / 74LS174, but with common Enable rather than common Master Reset. The SN54 / 74LS379 is a 4-Bit R.

  SN54LS378   SN54LS378






Part Number SN54LS378
Manufacturers Texas Instruments
Logo Texas Instruments
Description D-TYPE FLIP-FLOPS
Datasheet SN54LS378 DatasheetSN54LS378 Datasheet (PDF)

SN54LS377, SN54LS378, SN54LS379, SN74LS377, SN74LS378, SN74LS379 OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE SDLS167 – OCTOBER 1976 – REVISED MARCH 1988 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. •POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright © 1988, Texas Instruments Incorporated 1 SN54LS377, S.

  SN54LS378   SN54LS378







OCTAL D FLIP-FLOP

OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 / 74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54 / 74LS378 is a 6-Bit Register with a buffered common enable. This device is similar to the SN54 / 74LS174, but with common Enable rather than common Master Reset. The SN54 / 74LS379 is a 4-Bit Register with buffered common Enable. This device is similar to the SN54 / 74LS175 but features the common Enable rather then common Master Reset. • 8-Bit High Speed Parallel Registers • Positive Edge-Triggered D-Type Flip Flops • Fully Buffered Common Clock and Enable Inputs • True and Complement Outputs • Input Clamp Diodes Limit High Speed Termination Effects PIN NAMES LOADING (Note a) HIGH LOW E Enable (Active LOW) Input 0.5 U.L. 0.25 U.L. D0 – D3 CP Data Inputs Clock (Ac.


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