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SN54LS669 Datasheet

Part Number SN54LS669
Manufacturers Motorola Inc
Logo Motorola  Inc
Description SYNCHRONOUS 4-BIT UP/DOWN COUNTER
Datasheet SN54LS669 DatasheetSN54LS669 Datasheet (PDF)

SYNCHRONOUS 4-BIT UP/DOWN COUNTER The SN54 / 74LS669 is a synchronous 4-bit up/down counter. The LS669 is a 4-bit binary counter. For high speed counting applications, this presettable counter features an internal carry lookahead for cascading purposes. By clocking all flip-flops simultaneously so the outputs change coincident with each other (when instructed to do so by the count enable inputs and internal gating) synchronous operation is provided. This helps to eliminate output counting spikes.

  SN54LS669   SN54LS669






Part Number SN54LS669
Manufacturers Texas Instruments
Logo Texas Instruments
Description SYNCHRONOUS 4-BIT UP/DOWN COUNTER
Datasheet SN54LS669 DatasheetSN54LS669 Datasheet (PDF)

SN54LS668, SN54LS669, SN74LS668, SN74LS669 SYNCHRONOUS 4-BIT UP/DOWN COUNTERS SDLS192 – APRIL 1977 – REVISED MARCH 1988 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright © 1988, Texas Instruments Incorporated 1 SN54LS668, SN74LS668 SYNCHRONOUS 4-BIT UP/DOWN COUN.

  SN54LS669   SN54LS669







SYNCHRONOUS 4-BIT UP/DOWN COUNTER

SYNCHRONOUS 4-BIT UP/DOWN COUNTER The SN54 / 74LS669 is a synchronous 4-bit up/down counter. The LS669 is a 4-bit binary counter. For high speed counting applications, this presettable counter features an internal carry lookahead for cascading purposes. By clocking all flip-flops simultaneously so the outputs change coincident with each other (when instructed to do so by the count enable inputs and internal gating) synchronous operation is provided. This helps to eliminate output counting spikes, normally associated with asynchronous (ripple-clock) counters. The four master-slave flip-flops are triggered on the rising (positive-going) edge of the clock waveform by a buffered clock input. Circuitry of the load inputs allows loading with the carry-enable output of the cascaded counters. Because loading is synchronous, disabling of the counter by setting up a low level on the load input will cause the outputs to agree with the data inputs after the next clock pulse. Cascading counters for N-bit synchronous applications are provided by the carry look-ahead circuitry, without additional gating. Two count-enable inputs and a carry output help accomplish this function. Count-enable inputs (P and T) must both be low to count. The level of the up-down input determines the direction of the count. When the input level is low, the counter counts down, and when the input is high, the count is up. Input T is fed forward to enable the carry output. The carry output will now produce a low le.


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