SN54LS76A

SN54/74LS76A DUAL JK FLIP-FLOP WITH SET AND CLEAR The SN54/ 74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level of the J and K inputs will perform according to the Truth Table as long as minimum set-up times are observed. Input data is transferred to the outputs on the HIGH-to-LOW clock transitions. DUAL JK FLIP-FLOP WITH SET AND CLEAR LOW POWER SCHOTTKY MODE SELECT — TRUTH TABLE INPUTS OPERATING MODE SD Set Reset (Clear) *Undetermined Toggle Load “0” (Reset) Load “1” (Set) Hold L H L H H H H CD H L L H H H H J X X X h l h l K X X X h h l l Q H L H q L H q Q L H H q H L q OUTPUTS 16 1 J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 *Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. H,h = HIGH Voltage Level L,l = LOW Voltage Level X = Immaterial l, h (q) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the HIGH-to-LOW clock transition 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC LOGIC DIAGRAM LOGIC SYMBOL Q Q 16 1 CLEAR (CD) J SET (SD) K 4 K CP J C Q D 3 CLOCK (CP) VCC = PIN 5 GND = PIN 13 14 2 SD Q 15 12 6 9 K CP J C Q D 8 10 7 SD Q 11 FAST AND LS TTL DATA 5-79 SN54/74LS76A GUARANTEED OPERATING RANG...