SN54LV11A, SN74LV11A TRIPLE 3ĆINPUT POSITIVEĆAND GATES
D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical ...
SN54LV11A, SN74LV11A TRIPLE 3ĆINPUT POSITIVEĆAND GATES
D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
D Support Mixed-Mode
Voltage Operation on
All Ports
D Ioff Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101)
description/ordering information
These triple 3-input positive-AND gates are designed for 2-V to 5.5-V VCC operation.
The ’LV11A devices perform the Boolean function
Y + A B C or Y + A ) B ) C in positive logic.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
SCES345D − DECEMBER 2000 − REVISED APRIL 2005
SN54LV11A . . . J OR W PACKAGE SN74LV11A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
1A 1B 2A 2B 2C 2Y GND
1 2 3 4 5 6 7
14 VCC 13 1C 12 1Y 11 3C 10 3B 9 3A 8 3Y
SN54LV11A . . . FK PACKAGE (TOP VIEW)
VCC
2A
3 2 1 20 19 4 18
1Y
NC 5
17 NC
2B 6
16 3C
NC 7
15 NC
2C 8
14 3B
9 10 11 12 13
3A 1C
NC NC
GND 1A
2Y 1B
3Y
NC − No internal connection
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE PART NUMBER
TOP-SIDE MARKING
SOIC − D
Tube of 50 Reel of 2500...
