SN54LV165A

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN54LV165A, SN74LV165A SCLS402O – APRIL 1998 – REVISED NOVEMBER 2016 SNx4LV165A Parallel-Load 8-Bit Shift Registers 1 Features 1 2-V to 5.5-V VCC Operation Max tpd of 10.5 ns at 5 V Support Mixed-Mode Voltage Operation on All Ports Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 2 Applications IP Routers Enterprise Switches Access Control and Security: Access Keypads and Biometrics Smart Meters: Power Line Communication 3 Description The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation. When the devices are clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. The ’LV165A devices feature a clock-inhibit function and a complemented serial output, QH. Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and clock inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH accomplishes clocking, CLK INH must be changed to the high level only while CLK is high. Parallel ...